The present invention relates to a semiconductor memory device, more particularly, to a circuit configured to transport data during read and write operations in a semiconductor memory device.
A semiconductor memory device is used to store data and provide desired data. A write operation for storing data and a read operation for outputting a selected data among the stored data are main operations of the semiconductor memory device. A precharge operation for preparing the read and write operations is also provided in the case where the read and write operations are not performed. In a semiconductor memory device in which a capacitor is used as a data storage unit (e.g., dynamic random access memory (DRAM) device), a refresh operation is also performed to compensate for naturally occurring leakage of charges stored in the capacitor.
A semiconductor memory device includes unit cells, which are basic elements for data storage and are arranged in a matrix form to effectively input/output a large amount of data. The unit cells arranged in the matrix form are allocated individually at points where a plurality of word lines crossing horizontally intersect with a plurality of bit lines crossing vertically. Row addresses allocate the word lines, while column addresses allocate the bit lines. In general, when a read or write operation is performed, a row address is first input to select one of the word lines, and then a column address to select one of the bit lines. One unit cell corresponding to the selected word line and bit line is to be accessed to perform a read or write operation.
For effective configuration, a semiconductor memory device receives row addresses and column addresses through an address input pad, and uses input/output (IO) pads for data input and output. Data are output through the data IO pads during a read operation, and input through the data IO pads during a write operation. Because one data transport line exists between the unit cell and the data IO pads, a transport circuit for a write operation and another transport circuit for a read operation are arranged to transport data in a given direction during the read and write operations, respectively.
FIG. 1 is a block diagram illustrating data input and output of a conventional semiconductor memory device. The semiconductor memory device includes an output data transport block 10 and an input data transport block 20.
The output data transport block 10 includes an IO sense amplifier 11 and a global driver 12. The IO sense amplifier 11 is configured to sense signal levels of output data transported through local IO lines LIO and LIOb and amplify the sensed signal levels. The global driver 12 drives a global IO line GIO according to the data transported from the IO sense amplifier 11.
The input data transport block 20 includes a data transport unit 21, first and second local driver units 22 and 23, and a local IO line control unit 24. The data transport unit 21 is configured to receive the data transported through the global IO line GIO in response to a write control signal WTDDRVCON. The first and second local driver units 22 and 23 are configured to transport the data from the data transport unit 21 to the respective local IO lines LIO and LIOb. The local IO line control unit 24 is configured to control a precharge level of the local IO lines LIO and LIOb.
During a read operation, the IO sense amplifier 11 senses data transported through the local IO lines LIO and LIOb and amplifies the sensed data. The global driver 12 drives the amplified data to the global IO line GIO. The data transported through the global IO line GIO pass through a data output buffer and are output outside through an IO pad.
During a write operation, data transported through the IO pad, a data input buffer, and the global IO line GIO in sequence is input to the data transport unit 21. The data transport unit 21 senses a level of the data transported through the global IO line GIO and transports a first signal of a first level and a second signal of a second level corresponding to the sensed level of the data to the respective first and second local driver units 22 and 23. The local IO line control unit 24 controls the local lines LIO and LIOb to be precharged when the data are not provided to the local IO lines LIO and LIOb.
FIG. 2 illustrates a schematic circuit diagram of the output data transport block 10 illustrated in FIG. 1. The IO sense amplifier 11 senses voltage levels of signals provided to the local IO lines LIO and LIOb in response to a read control signal IOSACON, and amplifies voltage levels of two nodes A and B corresponding to the sensed signal voltage levels. According to the voltage levels at the nodes A and B, the IO sense amplifier 11 outputs signals D0 and D1b to the global driver 12. The global driver 12 drives the global IO line GIO in a pull-up or pull-down mode in response to the signals D0 and D1b. 
FIG. 3 illustrates a schematic circuit diagram of the input data transport block 20 illustrated in FIG. 1. The data transport unit 21 stores data transported through the global IO line GIO into first and second latches L1 and L2 when the write control signal WTDRVCON is input in a logically low level. The data stored into the first and second latches L1 and L2 are transported to third and fourth latches L3 and L4 when the write control signal WTDRVCON becomes a logically high level. The transported data at the third and fourth latches L3 and L4 are transported to the first and second local driver units 22 and 23. The first and second local driver units 22 and 23 transport the data transported by the third and fourth latches L3 and L4 to the respective local IO lines LIO and LIOb. When the data are not provided to the local IO lines LIO and LIOb, the local IO line control unit 24 controls voltage levels of the local IO lines LIO and LIOb to be precharged to a logically high level.
As described above, the conventional semiconductor memory device needs to be configured with the output data transport block 10 and the input data transport block 20 that receive data and transport the received data during the individual read and write operations in order to smoothly execute the read and write operations through one of the data transport lines, herein the global IO line GIO and the local IO lines LIO and LIOb.
During the execution of the read and write operations, the semiconductor memory device inputs multiple pieces of data in parallel and outputs the data, instead of inputting and outputting one piece of data at each time. For instance, assuming that 4 banks are provided in the case of ×16 DRAM, 16×4 numbers of global lines, 32×4 numbers of local IO lines, and 16×4 numbers of output data transport blocks IO and input data transport blocks 20 need to be arranged in the semiconductor memory device.
Another conventional semiconductor memory device is implemented with a pre-fetch operation in which 2-bit data or 4-bit data are fetched prior to inputting or outputting data. For this pre-fetch operation, this type of semiconductor memory device generally requires more data transport lines than the first mentioned conventional semiconductor memory device. However, those lines and transport units arranged to input and output data often occupy a large area. Also, the data transport lines need to be arranged close to the individual banks so as to reduce the load on the data transport lines. Because many data transport lines and data transport circuits are generally necessary, it may be difficult to effectively arrange the data transport lines and the data transport circuits.